Memory module and memory system having the same

ABSTRACT

A memory module includes a serial presence detector (SPD) configured to detect a module identification (ID) through at least one module position identification terminal, and generate at least one of the module ID and a register address corresponding to the module ID. A power management unit (PMU) is responsive to at least one of the module ID and the register address generated by the SPD. The PMU is configured to set an on-time point and/or an off-time point of an internal clock signal based on at least one of the module ID and the register address corresponding to the module ID, and further configured to generate at least one internal power supply voltage in response to the internal clock signal. A plurality of memory devices are also provided, which are configured to receive the at least one internal power supply voltage and perform an operation in response to command/address signals.

REFERENCE TO PRIORITY APPLICATION

This application claims priority from Korean Patent Application No.10-2019-0047980, filed Apr. 24, 2019, and Korean Patent Application No.10-2019-0090970, filed Jul. 26, 2019, the disclosures of which arehereby incorporated herein by reference.

BACKGROUND 1. Field

Devices and systems consistent with example embodiments relate to amemory module and a memory system including the same.

2. Description of Related Art

A memory system may generally include a plurality of memory slots, acontroller, and a power management unit (PMU), which are mounted on amain board. A memory module may be inserted into each of the pluralityof memory slots. However, recently, the memory module including thepower management unit has been developed. Accordingly, there is a needfor a technology of controlling the power management unit included ineach of the plurality of memory modules to stably generate internalpower supply voltages using an external power supply voltage.

SUMMARY

The example embodiments of the inventive concept are directed toproviding a memory module capable of stably generating internal powersupply voltages by a power management unit (PMU) included in a memorymodule, and a memory system having the same.

Aspects of the inventive concept should not be limited by the abovedescription, and other unmentioned aspects will be clearly understood byone of ordinary skill in the art from example embodiments describedherein.

According to example embodiments, there is provided a memory module,which includes a serial presence detector configured to detect a moduleidentification (ID) through at least one module position identificationterminal, and transmit the module ID (or a register addresscorresponding to the module ID). A power management unit is alsoprovided, which is configured to: communicate with the serial presencedetector over a local data communication channel, receive the module ID(or the register address corresponding to the module ID), set an on-timepoint and/or an off-time point of an internal clock signal based on themodule ID (or the register address corresponding to the module ID), andgenerate at least one internal power supply voltage in response to theinternal clock signal. A plurality of semiconductor memory devices arealso provided, which are configured to receive the at least one internalpower supply voltage, perform an operation in response tocommand/address signals, and store or output data.

According to additional embodiments, there is provided a memory module,which includes a power management unit configured to set an on-timepoint and/or an off-time point of an internal clock signal based on amodule ID, and generate at least on internal power supply voltage inresponse to the internal clock signal. A plurality of semiconductormemory devices are also provided, which are configured to receive the atleast one internal power supply voltage, perform an operation inresponse to command/address signals, and store or output data.

According to further embodiments of the invention, there is provided amemory system including: a main board, a plurality of memory slotsdisposed at a plurality of positions different from each other on themain board, a plurality of memory modules mounted in the plurality ofmemory slots, and a control unit. This control unit is configured toperform global data communication with the plurality of memory modules,transmit a command/address, and transmit and receive data. Each of theplurality of memory modules may include a respective power managementunit, which is configured to set an on-time point and/or an off-timepoint of an internal clock signal based on a corresponding module IDamong a plurality of different module IDs, and generate at least oneinternal power supply voltage in response to the internal clock signal.A plurality of semiconductor memory devices are also provided, which areconfigured to receive the at least one internal power supply voltage,perform an operation in response to the command/address, and store oroutput the data.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a configuration of a memory moduleaccording to an example embodiment of the inventive concept.

FIG. 2 is a block diagram illustrating a configuration of a serialpresence detector according to an example embodiment of the inventiveconcept.

FIG. 3 is a block diagram illustrating a configuration of a powermanagement unit according to an example embodiment of the inventiveconcept.

FIG. 4 is a block diagram illustrating a configuration of an internalclock signal generator according to an example embodiment of theinventive concept.

FIG. 5 is an operational timing diagram for describing an operation ofthe internal clock signal generator shown in FIG. 4.

FIG. 6 is a diagram illustrating a configuration of a voltage generatoraccording to an example embodiment of the inventive concept.

FIG. 7 is a table illustrating control data according to module IDs of aplurality of control data registers of a register unit according to anexample embodiment of the inventive concept.

FIG. 8 is an operational timing diagram for describing local datacommunication between a serial presence detector and a power managementunit according to an example embodiment of the inventive concept.

FIG. 9 is an operational timing diagram for describing local datacommunication between a serial presence detector and a power managementunit according to an example embodiment of the inventive concept.

FIG. 10 is an operational timing diagram for describing global datacommunication between an external device and a serial presence detectoraccording to an example embodiment of the inventive concept.

FIG. 11 is an operational timing diagram for describing local datacommunication between a serial presence detector and a power managementunit according to an example embodiment of the inventive concept.

FIG. 12 is a block diagram illustrating a configuration of a memorymodule according to an example embodiment of the inventive concept.

FIG. 13 is a block diagram illustrating a configuration of a powermanagement unit according to an example embodiment of the inventiveconcept.

FIG. 14 is an operational timing diagram for describing global datacommunication between an external device and a power management unitaccording to an example embodiment of the inventive concept.

FIG. 15 is a block diagram illustrating a configuration of a memorysystem according to an example embodiment of the inventive concept.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, a memory module and a memory system having the sameaccording to example embodiments will be described with reference to theaccompanying drawings.

FIG. 1 is a block diagram illustrating a configuration of a memorymodule according to an example embodiment of the inventive concept, amemory module 100 may include 4 n semiconductor memory devices M11 to M1n, M21 to M2N, M31 to M3 n, and M41 to M4 n, a module board 10, a serialpresence detector (SPD) 12, a power management unit (PMU) 14, atemperature sensor (TS) 16, and a register clock driver (RCD) 18. InFIG. 1, the 4 n semiconductor memory devices M11 to M1 n, M21 to M2N,M31 to M3 n, and M41 to M4 n, the serial presence detector 12, a powermanagement unit 14, a temperature sensor 16, and a register clock driver18 may be mounted on an upper surface (or a lower surface) of the mainboard 10. DQLP may represent left data terminals, DQRP may representright data terminals, CA1P may represent first command/addressterminals, CA2P may represent second command/address terminals, SAP mayrepresent serial address terminals, SCLP may represent a serial clocksignal terminal, and SDAP may represent serial data terminals.

A function of each of the blocks shown in FIG. 1 is described more fullyhereinbelow.

Then semiconductor memory devices M11 to M1 n may input and output datathrough some terminals of the left data terminals DQLP in response to afirst command/address signal ca11, and then semiconductor memory devicesM21 to M2 n may input and output data through the remaining terminals ofthe left data terminals DQLP in response to a second command/addresssignal ca12. The n semiconductor memory devices M31 to M3 n may inputdata and output data through some of the terminals of the right dataterminals DQRP in response to a third command/address signal ca21, andthe n semiconductor memory devices M41 to M4 n may input and output datathrough the remaining terminals of the right data terminals DQRP inresponse to a fourth command/address signal ca22. For example, when thememory module 100 includes 20 semiconductor memory devices M11 to M1 n,M21 to M2 n, M31 to M3 n, and M41 to M4 n (n=5), and each of the 20semiconductor memory devices M11 to Ml n, M21 to M2 n, M31 to M3 n, andM41 to M4 n inputs and outputs 4-bit data through 4 data terminals, thememory module 100 may input and output 80-bit data through 40 left dataterminals DQLP and 40 right data terminals DQRP.

The serial presence detector (SPD) 12 may perform global datacommunication (for example, data communication according to an I2C(Inter-Integrated Circuit) or I3C (Improved Inter-Integrated Circuit)communication protocol) through a channel including the serial clocksignal terminal SCLP and the serial data terminal SDAP. The serialpresence detector 12 may detect a passive element (for example, aresistor) connected to a module position identification terminal (MIDP),and generate a module identification (ID). For example, the serialpresence detector 12 may detect a current or a voltage of the moduleposition identification terminal MIDP, and generate the module ID.Unlike the configuration shown, the serial presence detector 12 maydetect voltages (for example, an external power supply voltage and/or aground voltage applied to the memory module 100) connected to at leasttwo module position identification terminals, and generate the moduleID. The serial presence detector 12 may perform local data communication(for example, data communication according to the I2C or I3Ccommunication protocol) with the power management unit 14, thetemperature sensor 16, and the register clock driver 18, through achannel including the local serial clock signal line LSCLL and the localserial data line LSDAL. The serial presence detector 12 may perform thelocal data communication with the power management unit 14 to transmitthe module ID or a register address corresponding to the module ID.

The power management unit 14 may generate a predetermined number ofinternal power supply voltages using an external power supply voltage,and perform the local data communication with the serial presencedetector 12. The power management unit 14 may set an on-time pointand/or an off-time point of an internal clock signal based on the moduleID transmitted from the serial presence detector 12. The powermanagement unit 14 may set the on-time point and/or the off-time pointof the internal clock signal based on the register address correspondingto the module ID transmitted from the serial presence detector 12.Although not shown, the power management unit 14 may apply thepredetermined number of internal power supply voltages to the 4 nsemiconductor memory devices M11 to M1 n, M21 to M2 n, M31 to M3 n, andM41 to M4 n, the serial presence detector 12, the temperature sensor 16,and the register clock driver 18.

The temperature sensor 16 may sense a temperature and perform the localdata communication with the serial presence detector 12. The registerclock driver 18 may input a first command/address applied through thefirst command/address terminals CA1P to generate the firstcommand/address signal ca11 and the second command/address signal ca12,and may input a second command/address applied through the secondcommand/address terminals CA2P to generate the third command/addresssignal ca21 and the fourth command/address signal ca22. Further, theregister clock driver 18 may perform the local data communication withthe serial presence detector 12. As can be seen from the abovedescription, when performing the local data communication, the serialpresence detector 12 may operate as a master, and the serial presencedetector 14, the temperature sensor 16, and the register clock driver 18may operate as slaves.

FIG. 2 is a block diagram illustrating a configuration of the serialpresence detector according to an example embodiment of the inventiveconcept, the serial presence detector 12 may include a global interfaceunit 12-10, a module position detector 12-12, a control logic unit12-14, a register unit 12-16, and a local interface unit 12-18.

A function of each of the blocks shown in FIG. 2 is described below.

The global interface unit 12-10 may input and output serial data SDA inresponse to a global serial clock signal SCL applied from the outside.For example, the global interface unit 12-10 may perform global datacommunication based on an I2C or I3C communication protocol. Further,the global interface unit 12-10 may convert the serial data SDA receivedin series into data da generated in parallel, or convert the data dareceived in parallel into the serial data SDA generated in series. Whenperforming the global data communication, the serial presence detector12 may operate as a slave.

The module position detector 12-12 may sense a passive element (forexample, a resistor (not shown)) connected to a module positionidentification terminal MIDP (refer to FIG. 1), and generate a module ID“mid”. When the passive element is connected to the module positionidentification terminal MIDP, the module position detector 12-12 maysense a current flowing through the module position identificationterminal MIDP or a voltage of the module position identificationterminal MIDP, and generate the module ID mid. When the module ID mid isreceived, the control logic unit 12-14 may generate a register addressadd indicating a module ID register, generate the module ID mid as datad, and store the module ID in a module ID register. When the module IDis received, the control logic unit 12-14 may generate the registeraddress of the module ID register of the power management unit 14 andthe module ID as data db. Alternatively, the control logic unit 12-14may generate the register address corresponding to the module ID of thepower management unit 14 as the data db. When the data da is received,the control logic unit 12-14 may determine whether both a local deviceID and a module ID included in the data da match both a correspondinglocal device ID (that is, a local device ID of the serial presencedetector 12, for example, 4-bit data “1010”) stored in a local device IDregister and a corresponding module ID (that is, a module ID of thememory module 100, for example, 3-bit data “010”) stored in the moduleID register, and if the two IDs match, the control logic unit 12-14 mayreceive the data da and generate a register address included in the datada as a register address add, and store the data d in the register ofthe register unit 12-16 corresponding to the register address add orreceive the data d output from the register of the register unit 12-16corresponding to the register address add to generate the data da. Ifonly the module IDs match and the local device IDs do not match, thecontrol logic unit 12-14 may receive the data da to generate the datada. That is, when the control logic unit 12-14 determines that the datada is related to other local devices (for example, the power managementunit 14, the temperature sensor 16, or the register clock driver 18) ofa corresponding memory module, the control logic unit 12-14 may receivethe data da to generate the data db.

The register unit 12-16 may include a plurality of registers including alocal device ID register and a module ID register, and the plurality ofregisters may be selected in response to the register address add tostore the data d, or output stored data as the data d. The local deviceID register may previously store the local device ID (for example,“1010”) of the serial presence detector 12, the local device ID (forexample, “1001”) of the power management unit 14, the local device ID(for example, “0010”) of the temperature sensor 15, and the local deviceID (for example, “1011”) of the register clock driver 18.

The local interface unit 12-18 may receive the data db, and output localserial data LSDA in response to the local serial clock signal LSCL.Further, the local interface unit 12-18 may receive the local serialdata LSDA in response to the local serial clock signal LSCL to generatethe data db. The local interface unit 12-18 may convert the data dbreceived in parallel into the local serial data LSDA generated inseries, or convert the local serial data LSDA received in series intothe data db generated in parallel.

FIG. 3 is a block diagram illustrating a configuration of a powermanagement unit according to an example embodiment of the inventiveconcept, and the power management unit 14 may include a local interfaceunit 14-10, a control logic unit 14-12, a register unit 14-14, aninternal clock signal generator 14-16, and a voltage regulator 14-18.

A function of each of the blocks shown in FIG. 3 will be describedbelow.

The local interface unit 14-10 may input and output the local serialdata LSDA in response to the local serial clock signal LSCL. Forexample, the local interface unit 14-10 may perform local serial datacommunication based on an I2C or I3C communication protocol. Further,the local interface unit 14-10 may convert the local serial data LSDAreceived in series into data da generated in series into data dcgenerated in parallel, or convert the data dc received in parallel intothe local serial data LSDA generated in series.

When the data dc is received, the local device ID included in the datadc matches a corresponding local device ID (for example, “1001”) storedin the local device ID register, and the module ID included in the datadc indicates a corresponding module ID (for example, “010”), the logiccontrol unit 14-12 may receive the data dc to generate the registeraddress included in the data dc as a register address addl, and storedata dl in a register corresponding to the register address addl orreceive the data dl output from the register corresponding to theregister address addl to generate the data dc. As one example, when thelocal device ID matches the corresponding local device ID, the module IDindicates the corresponding module ID, and the register address addl isa register address of the module ID register, the control logic unit14-12 may store the module ID in the module ID register, and outputcontrol data of a control data register corresponding to the module ID.As another example, when the local device ID matches the correspondinglocal device ID, and the module ID indicates the corresponding moduleID, and the register address addl is the register address of the controldata register corresponding to the module ID, the control logic unit14-12 may output control data stored in the control data register.

The register unit 14-14 may include a plurality of registers including acorresponding local device ID register, a module ID register, and aplurality of control data registers, and the plurality of registers maybe selected in response to the register address addl to store the datadl, or output stored data as the data dl. A plurality of pieces ofcontrol data may be previously stored in the plurality of control dataregisters. As one example, the plurality of control data registers maybe configured to output one of the plurality of pieces of control datain response to the module ID stored in the module ID register. Asanother example, the plurality of control data registers may beconfigured to generate one of the plurality of pieces of control data inresponse to the register address.

The internal clock signal generator 14-16 may set an on-time pointand/or an off-time point of the internal clock signal ICLK in responseto control data de. The voltage regulator 14-18 may include k internalpower supply voltage generators VR1 to VRk generating k internal powersupply voltages VR1 to VRk which are the same or different from eachother. Each of the k internal power supply voltages VR1 to VRk maygenerate the k internal power supply voltages V1 to Vk using (pumpingdown) an external power supply voltage (for example, 12V) applied fromthe outside. Each of the k internal power supply voltage generators VR1to VRk may be a buck converter.

FIG. 4 is a block diagram illustrating a configuration of an internalclock signal generator according to an example embodiment of theinventive concept, the internal clock signal generator 14-16 may includea ramp signal generator 20, a comparison voltage generator 22, a firstcomparator 24, a second comparator 26, and a latch 28. FIG. 5 is anoperational timing diagram for describing an operation of the internalclock signal generator shown in FIG. 4.

An operation of each of the blocks will be described below withreference to FIGS. 4 and 5.

The ramp signal generator 20 may generate a ramp signal Vramp. Thecomparison voltage generator 22 may generate a first comparison voltageVC1 and a second comparison voltage VC2 using an external power supplyvoltage in response to control data de. The first comparison voltage VC1is greater than the second comparison voltage VC2. The first comparator24 may generate a first clock signal CLK1 of increasing to a logic“high” level when a voltage of the ramp signal Vramp is equal to orgreater than the first comparison voltage VC1, and of decreasing to alogic “low” level when the voltage of the ramp signal Vramp is smallerthan the first comparison voltage VC1. The second comparator 26 maygenerate a second clock signal CLK2 of increasing to a logic “high”level when the voltage of the ramp signal Vramp is equal to or greaterthan the second comparison voltage VC2, and of decreasing to a logic“low” level when the voltage of the ramp signal Vramp is smaller thanthe second comparison voltage VC2.

The latch 28 may generate an internal clock signal ICLK of increasing toa logic “high” level in response to the first clock signal CLK1 which isat the logic “high” level, and of decreasing to a logic “low” level inresponse to the second clock signal CLK2 which is at the logic “high”level. The latch 28 may be an SR latch. In the internal clock signalgenerator 14-16 shown in FIG. 4, the first comparison voltage VC1 may bevariably set along an arrow direction shown in FIG. 5 and the secondcomparison voltage VC2 may be variably set along an arrow directionshown in FIG. 5 in response to the control data de. Accordingly, theon-time point of the first clock signal CLK1 and the on-time point ofthe second clock signal CLK2 may be variably set, and thus the on-timepoint and the off-time point of the internal clock signal ICLK may bevariably set.

As another example, the first comparison voltage VC1 may be variablyset, and the second comparison voltage VC2 may be fixed. Accordingly,the on-time point of the first clock signal CLK1 may be variably set andthe on-time point of the on-time point of the second clock signal CLK2may be fixed, and thus the on-time point of the internal clock signalICLK may be varied and the off-time point of the internal clock signalICLK may be fixed. Further, as another example, the first comparisonvoltage VC1 may be fixed and the second comparison voltage VC2 may bevariably set. Accordingly, the on-time point of the first clock signalCLK1 may be fixed and the on-time point of the second clock signal CLK2may be variably set, and thus the on-time point of the internal clocksignal ICLK may be fixed and the off-time point of the internal clocksignal ICLK may be variably set. That is, the internal clock signalgenerator 14-16 shown in FIG. 4 may variably set the on-time pointand/or the off-time point of the internal clock signal ICLK in responseto the control data de.

FIG. 6 is a diagram illustrating a configuration of a voltage generatoraccording to an example embodiment of the inventive concept, and thevoltage generator VR1 shown in FIG. 6 may include a high-side switchingtransistor Q1, a low-side switching transistor Q2, an inductor L, and acapacitor C.

Referring to FIG. 6, the internal clock signal ICLK may be applied tothe high-side switching transistor Q1, an internal clock signal ICLKLmay be applied to the low-side switching transistor Q2. The high-sideswitching transistor Q1 may be turned on in response to the internalclock signal ICLK which is at a logic “high” level, and the low-sideswitching transistor Q2 may be turned on in response to the internalclock signal ICLKL which is at the logic “high” level. The voltagegenerator shown in FIG. 6 illustrates a well-known buck converter, andthe buck converter may perform a switching operation in response theinternal clock signals ICLK and ICLKL, and generate an internal powersupply voltage V1 using (pumping down) the external power supply voltageVdd.

FIG. 7 is a table illustrating control data according to module IDs of aplurality of control data registers of a register unit according to anexample of the inventive concept.

Referring to FIG. 7, 8 different control data C1 to C8 may be stored in8 control data registers corresponding to 8 module IDs (for example,“000”, “001”, “010”, “011”, “100”, “101”, “110”, and “111”). The 8control data registers may be configured to output corresponding controldata according to the module ID stored in the module ID register.Alternatively, the 8 control data registers may be configured to outputthe 8 different control data C1 to C8 in response to 8 differentregister addresses corresponding to the 8 module IDs. Each of theplurality of register addresses may be a predetermined number of bits ofdigital data (for example, 8-bit data or more), and each of theplurality of pieces of control data D1 to D8 may be a predeterminednumber of bits of digital data (for example, 8-bit or more data).

Referring to FIGS. 4 to 7, in the internal clock signal generator 14-16,the first comparison voltage VC1 and/or the second comparison voltageVC2 may be varied in response to the 8 different control data C1 to C8,and thus the on-time point and/or the off-time point of the internalclock signal ICLK may be variably set. For example, the internal clocksignal generator 14-16 may generate the internal clock signal ICLKhaving a basic frequency in response to the control data C5, differentlyadvance the on-time point and/or the off-time point of the internalclock signal ICLK in response to the control data C6 to C8, anddifferently delay the on-time point and/or the off-time point of theinternal clock signal ICLK in response to the control data C1 to C4. Inthis case, the basic frequency of the internal clock signal ICLK may bemaintained or varied in response to the control data C1 to C8.

FIG. 8 is an operational timing diagram for describing local datacommunication between a serial presence detector and a power managementunit PMU according to an example embodiment of the inventive concept,and is a diagram for describing an operation in which the serialpresence detector 12 writes a module ID to the power management unit 14according to an I2C protocol.

Referring to FIG. 8, when the module ID mid is received, the serialpresence detector 12 may perform the local data communication fortransmitting the module ID mid to the power management unit 14.

First, the serial presence detector 12 may transmit a start signal STARTto the power management unit 14. The serial presence detector 12 maytransmit an 8-bit local device address, that is, a 4-bit local device IDI6 to I3 (for example, the local device ID of the power management unit14, “1001”)+a 3-bit module ID I2 to I0 (for example, “111”) indicatingto be a corresponding module ID (for example, “010”)+one-bit writecommand (for example, “0” indicating to be a write command) as the localserial data LSDA by one bit in response to a local serial clock signalLSCL. The power management unit 14 may receive the local device address,and when the local device address includes the corresponding localdevice ID and a module ID indicating to be the corresponding module ID,transmit a reception acknowledgement signal ACK to the serial presencedetector 12 as the local serial data LSDA.

Next, the serial presence detector 12 may transmit an 8-bit registeraddress A7 to AO, for example, the register address of the module IDregister of the register unit 14-14 shown in FIG. 3, to the powermanagement unit 14 as the local serial data LSDA by one bit in responseto the local serial clock signal LSCL. When the register address isreceived, the power management unit 14 may transmit a receptionacknowledgement signal ACK to the serial presence detector 12.

Lastly, the serial presence detector 12 may transmit data D7 to D0including the 3-bit module ID D2 to D0, for example, “00000” +the 3-bitmodule ID (for example, “010”) to the power management unit PMU 14 asthe local serial data LSDA by one bit in response to the local serialclock signal LSCL. When the module ID is received, the power managementunit 14 may transmit a reception acknowledgement signal ACK to theserial present detector 12. The power management unit 14 may store thedata D7 to D0 in the module ID register of the register unit 14-14. Thepower management unit PMU 14 may generate the data D7 to D0 stored inthe module ID register or the control data de stored in the control dataregister according to the module ID D2 to D0.

The serial presence detector 12 may end the communication bytransmitting a reception non-acknowledgement signal NACK and a stopsignal STOP to the power management unit 14 after transmitting the dataD7 to D0 to the power management unit 14. According to the exampleembodiment shown in FIG. 8, when the serial presence detector 12transmits the module ID to the power management unit PMU 14, the powermanagement unit 14 may generate the control data de from the controldata register corresponding to the module ID.

FIG. 9 is an operational timing diagram for describing local datacommunication between a serial presence detector and a power managementunit according to an example embodiment of the inventive concept, and isa diagram for describing an operation in which the serial presencedetector 12 reads control data from the power management unit 14according to an I2C protocol.

Referring to FIG. 9, when the module ID mid is received, the serialpresence detector 12 may transmit a start signal START to the powermanagement unit 14. The serial presence detector 12 may transmit an8-bit local device address, that is, a four-bit local device ID I6 to I3(for example, “1001”)+a 3-bit module ID (for example, “111”) indicatingto be a corresponding module ID (for example, “010”)+1-bit write command(for example, “0”) to the power management unit 14 as the local serialdata LSDA by one bit in response to the local serial clock signal LSCL.The power management unit 14 may receive the local device address, andwhen the local device address includes the corresponding local device IDand the module ID indicating to be the corresponding module ID, transmita reception acknowledgement signal ACK to the serial presence detector12 as the local serial data LSDA.

Next, the serial presence detector 12 may transmit an 8-bit registeraddress A7 to AO, for example, a register address corresponding to acorresponding module ID among the register addresses of the plurality ofcontrol data registers of the register unit 14-14 shown in FIG. 3 to thepower management unit 14 as the local serial data LSDA by one bit inresponse to the local serial clock signal LSCL. When the registeraddress is received, the power management unit 14 may transmit areception acknowledgement signal ACK to the serial presence detector 12as the local serial data LSDA.

Next, the serial presence detector 12 may transmit a restart signal RSTART to the power management unit 14. The serial presence detector 12may an 8-bit local device address, that is, a 4-bit local device addressI6 to I3 (for example, “1001”)+a 3-bit module ID I2 to I0 (for example,“111) indicating to be a corresponding module ID (for example,“010”)+1-bit read command (for example, “1” indicating a read command)to the power management unit PMU 14 as the local serial data LSDA by onebit in response to the local serial clock signal LSCL. When the registeraddress is received, the power management unit 14 may transmit areception acknowledgement signal ACK to the serial presence detector 12as the local serial data LSDA.

The power management unit 14 may transmit a reception acknowledgementsignal ACK to the serial presence detector 12. The power management unit14 may generate control data de from one selected among the plurality ofcontrol data registers in response to the register address. Accordingly,the on-time point and/or the off-time point of the internal clock signalICLK may be set. The power management unit 14 may transmit data D7 to D0corresponding the control data de to the serial presence detector 12.

The serial presence detector 12 may transmit a receptionnon-acknowledgement signal NACK and a stop signal STOP after receivingthe data D7 to D0 from the power management unit 14, and end thecommunication.

According to the example embodiment shown in FIG. 9, when the serialpresence detector 12 transmits the register address corresponding to themodule ID to the power management unit 14, the power management unit 14may generate the control data de from the control data registercorresponding to the register address.

FIG. 10 is an operational timing diagram for describing global datacommunication between an external device and a serial presence detectoraccording to an example embodiment of the inventive concept, forexample, and is a diagram for describing an operation in which theexternal device transmits data to the serial presence detector 12.

Referring to FIG. 10, the external device may transmit a start signalSTART to the serial presence detector 12. The external device maytransmit an 8-bit local device address, that is, a 4-bit local device IDI6 to I3 (for example, “1001”)+a 3-bit corresponding module ID I2 to I0(for example, “010”)+1-bit write command (for example, “0”) to theserial present detector 12, as global serial data SDA by one bit inresponse to a global serial clock signal SCL. The serial presencedetector 12 may receive the local device address, and when the localdevice address includes the corresponding local device ID and thecorresponding module ID, transmit a reception acknowledgement signal ACKto the external device as the global serial data.

Next, the external device may transmit an 8-bit register address A7 toAO, for example, a register address corresponding to a correspondingmodule ID among register addresses of the plurality of control dataregisters of the register unit 14-14 shown in FIG. 3 to the serialpresence detector 12 as the global serial data SDA by one bit inresponse to the global serial clock signal SCL. When the registeraddress is received, the serial presence detector 12 may transmit areception acknowledgement signal ACK to the external device as theglobal serial data SDA.

Next, the external device may transmit a restart signal R START to theserial presence detector 12. The external device may transmit an 8-bitlocal device address, that is, a 4-bit local device ID I6 to I3 (forexample, “1001”)+a 3-bit corresponding module ID (for example,“010”)+1-bit read command (for example, “1” indicating a read command)to the serial presence detector 12 as the global serial data SDA by onebit in response to the global serial clock signal SCL. When the registeraddress is received, the serial presence detector 12 may transmit areception acknowledgement signal ACK to the external device as theglobal serial data SDA.

FIG. 11 is an operational timing diagram for describing local datacommunication between a serial presence detector and a power managementunit according to an example embodiment of the inventive concept, forexample, is a diagram for describing an operation in which the serialpresence detector 12 transmits data related to the power management unit14 transmitted from the external device to the power management unit 14.

The operational timing diagram shown in FIG. 11 may be the same as thatshown in FIG. 9, and will be easily understood with reference to thedescription of FIG. 9 described above.

According to the example embodiments shown in FIGS. 10 and 11, theexternal device may transmit the register address corresponding to themodule ID to the serial presence detector 12, the serial presencedetector 12 may the register address to the power management unit 14,and the power management unit 14 may generate the control data de fromthe control data register corresponding to the register address.

FIG. 12 is a block diagram illustrating a configuration of a memorymodule according to an example embodiment of the inventive concept, andthe memory module 100′ shown in FIG. 12 may be configured to exclude thepower management unit 12 of the memory module 100 shown in FIG. 1 andinclude a power management unit 14′ instead of the power management unit14 shown in FIG. 1.

Referring to FIG. 12, the power management unit 14′ may perform theglobal data communication according to a serial data communicationprotocol through a channel including the serial clock signal terminalSCLP and the serial data terminal SDAP. The power management unit 14′may detect a passive element (for example, a resistor) connected to amodule position identification terminal MIDP, and generate a module IDmid. The power management unit 14′ may detect a current or a voltage ofthe module position identification terminal MIDP, and generate themodule ID mid. Unlike the configuration shown in FIG. 12, the powermanagement unit 14′ may detect voltages connected at least two moduleposition identification terminals (for example, an external power supplyvoltage and/or a ground voltage applied to the memory module 100′), andgenerate the module ID mid. The power management unit 14′ may performthe local data communication with the temperature sensor 16, and theregister clock driver 18 through a channel including the local serialclock signal line LSCLL and the local serial data line LSDAL.

The power management unit 14′ may generate a predetermined number ofinternal power supply voltages using the external power supply voltage.When the module ID mid is received, the power management unit 14′ maystore the module ID in the module ID register. The power management unit14′ may set the on-time point or/and the off-time point of the internalclock signal ICLK based on the module ID stored in the module IDregister. Alternatively, the power management unit 14′ may set theon-time point or/and the off-time point of the internal clock signalICLK based on the register address corresponding to the module ID.

Although not shown, the power management unit 14′ may apply thepredetermined number of internal power supply voltages to the 4 nsemiconductor memory devices M11 to M1 n, M21 to M2 n, M31 to M3 n, andM41 to M4 n, the temperature sensor 16, and the register clock driver18.

FIG. 13 is a block diagram illustrating a configuration of a powermanagement unit according to an example embodiment of the inventiveconcept, and the power management unit 14′ may include a globalinterface unit 14-10′, a control logic unit 14-12′, a register unit14-14′, an internal clock signal generator 14-16′, a voltage regulator14-18′, a module position detector 14-20′, and a local interface unit14-22′.

A function of each of the blocks shown in FIG. 13 will be describedhereinbelow.

The global interface unit 14-10′, the control logic unit 14-12′, theregister unit 14-14′, and the module position detector 14-20′ mayperform the same function as the global interface unit 12-10, thecontrol logic unit 12-14, the register unit 12-16, and the moduleposition detector 12-12 shown in FIG. 2, respectively.

The internal clock signal generator 14-16′, and the voltage regulator14-16′ may perform the same function as the internal clock signalgenerator 14-16, and the voltage regulator 14-18 shown in FIG. 3,respectively.

That is, the power management unit 14′ shown in FIG. 13 may have aconfiguration in which both the serial presence detector 12 shown inFIG. 2 and the power management unit 14 shown in FIG. 3 are integrated.Accordingly, the power management unit 14′ may perform the local datacommunication with the serial presence detector 12 and not adjust theon-time point and/or the off-time point of the internal clock signalICLK, and when the module ID mid is received, set the on-time pointand/or the off-time point of the internal clock signal ICLK in responseto the control data de generated according to the module ID mid or theregister address corresponding to the module ID mid. The powermanagement unit 14′ may directly perform the global data communicationwith the external device, and receive the register address correspondingto the module ID mid and set the on-time point and/or the off-time pointof the internal clock signal ICLK in response to the control data degenerated according to the register address.

When the module ID mid is received, the control logic unit 14-12′ maygenerate the register address of the module ID register as an addressaddl, and generate the module ID mid as data d. As another example, whenthe module ID mid is received, the control logic unit 14-12′ maygenerate the register address corresponding the module ID mid as theaddress addl. Further, as another example, when the data da is received,the control logic unit 14-12′ may generate a register address of oneamong the plurality of control data registers included in the data da asthe address addl.

The register unit 14-14′ may store the module ID in the module IDregister, and generate one among the plurality of pieces of control dataas the control data de in response to the module ID. As another example,the register unit 14-14′ may generate the control data de from thecontrol data register corresponding to the register address.

The internal clock signal generator 14-16′ may set the on-time pointand/or the off-time point of the internal clock signal ICLK in responseto the control data de.

FIG. 14 is an operational timing diagram for describing global datacommunication between an external device and a power management unitaccording to an example embodiment of the inventive concept, forexample, and is a diagram for describing an operation in which theexternal device reads data from the power management unit 14′ accordingto an I2C protocol.

The operational timing diagram shown in FIG. 14 may be the same as thatshown in FIG. 11 when excluding that the external device transmits notthe module ID (for example, “111”) indicating to be a correspondingmodule ID (for example, “010”) but the corresponding module ID (forexample, “010”) when transmitting the local device address to the powermanagement unit 14′. Accordingly, the power management unit 14′ mayoutput the control data de from the control data register correspondingto the register address among the plurality of control data registers ofthe register unit 14-14′. The power management unit 14′ may set theon-time point and/or the off-time point of the internal clock signalICLK according to the control data de. Furthermore, the power managementunit 14′ may transmit the data D7 to D0 corresponding to the controldata de to the external device, and the external device may transmit areception non-acknowledgement signal NACK and a stop signal STOP afterreceiving the data D7 to D0, and end the communication.

FIG. 15 is a block diagram illustrating a configuration of a memorysystem according to an example embodiment of the inventive concept, andthe memory system 200 may include a control unit 30, i module slots MS1to MSi, and i memory modules MD1 to MDi, which are mounted on a mainboard 20.

Referring to FIG. 15, the memory system 200 may include i module IDresistors R1 to Ri connected to the i module slots MS1 to MSi. The imodule ID resistors R1 to Ri may be connected to an external powersupply voltage Vdd line arranged on the main board 20, and havedifferent resistances. The i module ID resistors R1 to Ri may beconnected to the module position identification terminals MIDP of the imemory modules MD1 to MDi, respectively. The control unit 30 may includea global interface unit 21, and a memory controller 34. Left data linesDQLL, first command/address lines CA1L, second command/address linesCA2L, right data lines DQRL, a global serial data line GSDAL, and aglobal serial clock signal line GSCLL may be arranged on the main board20.

Although not shown, the left data lines DQLL, the first command/addresslines CA1L, the second command/address lines CA2L, and the right datalines DQRL may be commonly connect to the left data terminals DQLP, thefirst command/address terminals CA1P, the second command/addressterminals CA2, and the right data terminals DQRP, respectively, of eachof the i memory modules MD1 to MDi. Further, the global serial data lineGSDAL, and the global serial clock signal line GSCLL may be commonlyconnected to the serial data terminal SDAP and the serial clock signalterminal SCKP, respectively, of each of the i memory modules MD1 to MDi.

Referring to FIG. 15, when each of the i memory modules MD1 to MDi ismounted in a corresponding module slot MS1, MS2, . . . , or MSi, each ofthe i memory modules MD1 to MDi may detect a corresponding module IDresistor R1, R2, . . . , or Ri connected to a corresponding moduleposition identification terminal MIDP, and identify a correspondingmodule ID. For example, when each of 8 memory modules MD1 to MD8 aremounted in the corresponding module slot MS1, MS2, . . . , or MS8, eachof the 8 memory modules MD1 to MD8 may identify “000”, “001”, “010”,“011”, “100”, “101”, “110”, or “111” as the corresponding module ID.

The i memory modules MD1 to MDi shown in FIG. 15 may have theconfiguration and perform the operation described above with referenceto FIGS. 1 to 11, and when the module ID mid is received, the serialpresence detector 12 may perform the local data communication with thepower management unit 14 to transmit the module ID or the registeraddress corresponding to the module ID, and the power management unit 14may generate the control data de according to the module ID or theregister address corresponding to the module ID. Alternatively, theglobal data communication and the local data communication are performedbetween the control unit 30, the serial presence detector 12, and thepower management unit 14, and the register address is transmitted to thepower management unit 14, and thus the power management unit 14 maygenerate the control data de. Accordingly, the on-time point and/or theoff-time point of the internal clock signals ICLK of the i memorymodules MD1 to MDi may be differently set.

Further, the i memory modules MD1 to MDi shown in FIG. 15 may have theconfiguration and perform the operation described above with referenceto FIGS. 12 to 14, and when the module ID mid is received, the powermanagement unit 14′ may generate the control data de according to themodule ID or the register address corresponding to the module ID.Alternatively, the global data communication is performed between thecontrol unit 30 and the power management unit 14′, and the registeraddress is transmitted to the power management unit 14′, and thus thepower management unit 14′ may generate the control data de. Accordingly,the on-time point and/or the off-time point of the internal clocksignals ICLK of the i memory modules MD1 to MDi may be differently set.

Referring to FIG. 15, since the i memory modules MD1 to MDi may sharethe global serial data line GSDAL and the global serial clock signalline GSCLL, a total of i global data communications may be sequentiallyperformed to generate the control data de of the i memory modules MD1 toMDi.

However, unlike the configuration shown, the memory system may have aconfiguration in which the global serial data line GSDAL is commonlyconnected to the i memory modules MD1 to MDi and i global serial clocksignal lines GSCLL is connected to the i memory modules MD1 to MDi,respectively, and one global data communication may be performed togenerate the control data de of the i memory modules MD1 to MDi.

As a result, the on-time points and/or the off-time points of theinternal clock signals ICLK of the i memory modules MD1 to MDi may bedifferently set, and thus an operating time points of the voltageregulators 14-18 or 14-18″ of the power management units 14 or 14′ maybe differ from each other. Accordingly, a drop of the external powersupply voltage occurring since the operating time points of the voltageregulators 14-18 or 14-18″ of the power management units 14 or 14′ arethe same may not occur. Therefore, the internal power supply voltagesmay be stably generated.

According to the example embodiments described above, an example inwhich the module position detector generates the module ID is described,however, there may be an example of not including the module positiondetector. In this case, the control unit may transmit a correspondingmodule ID of each of the i memory modules to each of the i memorymodules.

According to the example embodiments described above, an example whichthe module position detector generates the module ID according to thepassive element connected to one module position identification terminalMIDP is described, however, the module position detector may generatethe module ID by detecting voltages connected to at least two moduleposition identification terminals. For example, when there are 3 moduleposition identification terminals, 8 different module IDs may begenerated by detecting at least two voltages (for example, a powersupply voltage and a ground voltage) connected to the 3 module positionidentification terminals.

According to the example embodiments described above, the memory modulemay stable generate the internal power supply voltages by varying theon-time point and/or the off-time point of the internal clock signalbased on the module ID. Further, the memory system having the pluralityof memory modules may stably generate the internal power supply voltagesby differently controlling the on-time points and/or the off-time pointsof the internal clock signals of the plurality of power management unitsincluded in the plurality of memory modules. Accordingly, reliability ofan operation of the memory module and the memory system having the samemay be ensured.

While the embodiments of the inventive concept have been described withreference to the accompanying drawings, it should be understood by thoseskilled in the art that various modifications may be made withoutdeparting from the scope of the inventive concept and without changingessential features thereof. Therefore, the above-described embodimentsshould be considered in a descriptive sense only and not for purposes oflimitation.

What is claimed is:
 1. A memory module, comprising: a serial presencedetector (SPD) configured to detect a module identification (ID) throughat least one module position identification terminal, and generate atleast one of the module ID and a register address corresponding to themodule ID; a power management unit (PMU) responsive to at least one ofthe module ID and the register address generated by the SPD, the PMUconfigured to set an on-time point and/or an off-time point of aninternal clock signal based on at least one of the module ID and theregister address corresponding to the module ID, and further configuredto generate at least one internal power supply voltage in response tothe internal clock signal; and a plurality of semiconductor memorydevices configured to receive the at least one internal power supplyvoltage and perform an operation in response to command/address signals.2. The memory module of claim 1, further comprising: a temperaturesensor (TS) communicatively coupled to the SPD; and a register clockdriver (RCD) communicatively coupled to the SPD, the RCD configured toreceive and transmit the command/address signals to the plurality ofsemiconductor memory devices.
 3. The memory module of claim 2, whereinthe SPD is communicatively coupled by a local data communication channelto the PMU, RCD and TS; and wherein the local data communication channeltransmits at least one of the module ID and the register addresscorresponding to the module ID in series in response to a local serialclock signal.
 4. The memory module of claim 1, wherein the PMUcomprises: a register unit including a module ID register for storingthe module ID, and a plurality of control data registers for storing aplurality of pieces of different control data corresponding to aplurality of different module IDs; and an internal clock signalgenerator configured to generate the internal clock signal having theon-time point and/or the off-time point set in response to the controldata generated from one corresponding to the at least one of the moduleID and the register address corresponding to the module ID among theplurality of control data registers.
 5. The memory module of claim 1,wherein the SPD is configured to support global data communication withan external device, receive the register address corresponding to themodule ID, perform local data communication with the PMU, and transmitthe register address corresponding to the module ID.
 6. The memorymodule of claim 5, wherein the PMU comprises: a register unit includinga module ID register for storing the module ID, and a plurality ofcontrol data registers for storing a plurality of pieces of differentcontrol data corresponding to a plurality of different module IDs; andan internal clock signal generator configured to generate the internalclock signal having the on-time point and/or the off-time point set inresponse to the control data generated from one corresponding to theregister address corresponding to the module ID among the plurality ofcontrol data registers.
 7. The memory module of claim 6, wherein theglobal data communication provides the register address corresponding tothe module ID in series, in response to a global serial clock signal. 8.A memory module, comprising: a power management unit (PMU) configured toset an on-time point and/or an off-time point of an internal clocksignal based on a module ID, and generate at least one internal powersupply voltage in response to the internal clock signal; and a pluralityof semiconductor memory devices configured to receive the at least oneinternal power supply voltage and perform an operation in response tocommand/address signals.
 9. The memory module of claim 8, furthercomprising: a temperature sensor (TS) communicatively coupled to thePMU; and a register clock driver (RCD) communicatively coupled to thePMU, the RCD configured to receive and transmit the command/addresssignals to the plurality of semiconductor memory devices.
 10. The memorymodule of claim 8, wherein the PMU detects the module ID through atleast one module position identification terminal, and generates atleast one of the module ID and a register address corresponding to themodule ID.
 11. The memory module of claim 10, wherein the PMU comprises:a register unit including a plurality of control data registers forstoring a plurality of pieces of different control data corresponding toa plurality of different module IDs; and an internal clock signalgenerator configured to generate the internal clock signal having theon-time point and/or the off-time point set in response to the controldata generated from one corresponding to the at least one of the moduleID and the register address corresponding to the module ID among theplurality of control data registers.
 12. The memory module of claim 8,wherein the PMU is configured to support global data communication withan external device, and receive a register address corresponding to themodule ID.
 13. The memory module of claim 12, wherein the PMU comprises:a register unit including a plurality of control data registers forstoring a plurality of pieces of different control data corresponding toa plurality of different module IDs; and an internal clock signalgenerator configured to generate the internal clock signal having theon-time point and/or the off-time point set in response to the controldata generated from one corresponding to the register addresscorresponding to the module ID among the plurality of control dataregisters.
 14. A memory system, comprising: a main board having aplurality of memory slots therein; a plurality of memory modules mountedin the plurality of memory slots; and a control unit configured toperform global data communication with the plurality of memory modules,transmit a command/address, and transmit and receive data; wherein eachof the plurality of memory modules comprises: a power management unit(PMU) configured to set an on-time point and/or an off-time point of aninternal clock signal based on a corresponding module ID among aplurality of module IDs different from each other, and generate at leastone internal power supply voltage in response to the internal clocksignal; and a plurality of semiconductor memory devices configured toreceive the at least one internal power supply voltage, and perform anoperation in response to the command/address.
 15. The memory system ofclaim 14, wherein each of the plurality of memory modules furthercomprises: a serial presence detector (SPD) configured to transmit atleast one of the module ID and a register address corresponding to themodule ID by performing local data communication with the PMU whendetecting the module ID through at least one module positionidentification terminal, or transmit the register address correspondingto the module ID by performing the local data communication with the PMUwhen receiving the register address corresponding to the module ID byperforming the global data communication.
 16. The memory system of claim15, wherein the local data communication transmits the at least one ofthe module ID and the register address corresponding to the module ID inseries in response to a local serial clock signal, and wherein theglobal data communication transmits the register address correspondingto the module ID in series in response to a global serial clock signal.17. The memory system of claim 15, wherein each of the plurality ofmemory modules comprises: a temperature sensor configured to sense atemperature, and perform the local data communication with the SPD; anda register clock driver configured to receive the command/address totransmit a command/address signal to the plurality of semiconductormemory devices, and perform the local data communication with the SPD.18. The memory system of claim 14, wherein the PMU is configured togenerate the at least of the module ID and the register addresscorresponding to the module ID when detecting the module ID through atleast one module position identification terminal, or generate theregister address corresponding to the module ID when receiving theregister address corresponding to the module ID by performing the globaldata communication.
 19. The memory system of claim 18, wherein each ofthe plurality of memory modules comprises: a temperature sensorconfigured to sense a temperature, and perform local data communicationwith the PMU; and a register clock driver configured to receive thecommand/address to transmit a command/address signal to the plurality ofsemiconductor memory devices, and perform the local data communicationwith the PMU.
 20. The memory system of claim 14, wherein the PMU furthercomprises: a register unit including a module ID register for storingthe module ID, and a plurality of control data registers for storing aplurality of pieces of control data different from each othercorresponding to a plurality of module IDs; and an internal clock signalgenerator configured to generate the internal clock signal having theon-time point and/or the off-time point set in response to the controldata generated from one corresponding to the at least of the module IDand the register address corresponding to the module ID among theplurality of control data registers.